CEC220 FINAL PROJECT (Digital circuits)

CEC220 FINAL PROJECT (Digital circuits)Engine Controller Design In this project, you will have to design a complete four-strokefour-cylinder engine controller in VHDL. This controller willwork under the assumption of having an electronically drivenvalvetrain and input from a crank position sensor.A typical four-stroke engine has four “states”, called strokes :intake, compression, power, and exhaust. These four strokesoccur over two revolutions of the crankshaft, with each stroketaking half a revolution. The operation of a single cylinder isillustrated in the figure below (components marked in red areengaged):
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EMBRY-RIDDLE AERONAUTICAL UNIVERSITY
1
CEC220 FINAL PROJECT
Engine Controller Design (10% of final grade)
Due: W 25-Apr-2018 (PC04 NLT 1300, PC05 NLT 1400;
Code: Canvas as ZIP file; Hardcopy of code and simulations: in class;
NO LATE SUBMISSIONS ACCEPTED FOR ANY REASON;
Failure to submit either the code or hardcopy will constitute a 50% grade deduction)
F.1 BACKGROUND
In this project, you will have to design a complete four-stroke
four-cylinder engine controller in VHDL. This controller will
work under the assumption of having an electronically driven
valvetrain and input from a crank position sensor.
A typical four-stroke engine has four “states”, called strokes:
intake, compression, power, and exhaust. These four strokes
occur over two revolutions of the crankshaft, with each stroke
taking half a revolution. The operation of a single cylinder is
illustrated in the figure below (components marked in red are
engaged):
On stroke 2 (compression), the piston is pushed upward,
compressing the air-fuel mixture. At this point, both valves
are closed.
The spark plug (SP) fires on stroke 3 (power), igniting the
compressed air-fuel mixture and generating power to turn the
crankshaft. Both valves are closed during this period.
In the final state, the exhaust valve (VE) opens, venting the
exhaust fumes from the combustion process out of the engine.
TDC
ADVANCE
RETARD
VI = 1
FI = 1
spark
plug
SP = 1
CO
N
SP = 0
M
CO
piston
AUST
XH
MP RE S S I
VE
VO = 1
E
VI
VO = 0
I N TA K E
exhaust
ST I ON
intake
BU
O
fuel injector
crankshaft
VI = 0
FI = 0
(a) stroke 1, intake
(b) stroke 2, compression
Fig. 2: Engine cycle, annotated with the individual component
on and off states (VI: intake valve, VO: exhaust valve, SP: spark
plug, and FI: fuel injectors). TDC indicates the top dead center
position.
(c) stroke 3, power
(d) stroke 4, exhaust
Fig. 1: Illustration of a single cylinder operation in a typical
four-stroke engine.
In the first state (intake), the intake valve (VI) opens and
the fuel injector (FI) fires, delivering fuel and air into the
combustion chamber.
© Akhan Almagambetov
04/06/2018 Embry-Riddle Aeronautical University (Prescott, AZ)
The process above repeats, timed differently across four cylinders of the engine (in a four cylinder engine). Since there are
four strokes, the crankshaft has four possible positions that can
be detected by the crankshaft position sensor (CPS). Note that
the CPS simply outputs 12 pulses per a single crankshaft
revolution, with first pulse corresponding to the top dead
center position (see below). The engine controller should
synchronize valve actuations, spark plugs, and fuel injectors.
In Fig. 2, above, top dead center positioning refers to the red
timing marks on the timing belt and the camshaft sprocket
being aligned, as illustrated in Fig. 3. In a typical four-cylinder
engine, this would result in the following piston positioning
across the four cylinders (cyls. 1 and 4 would be on stroke 3,
while cyls. 2 and 3 would be on stroke 1), shown in Fig. 4.
2
ENGINE CONTROLLER DESIGN
F.2 DESIGN
timing alignment mark
camshaft
sprocket
timing belt
Your goal is to design a four-cylinder engine controller in
VHDL, as well as a corresponding testbench that showcases
the full functionality of your design.
Some of the entities should be separate, as given in Fig. 5,
below. Note that the ports on the entities in the diagram should
be the only ports that you use. Any deviation from what’s
listed below will result in heavy penalties.
belt tensioner
bearing
intermediate
shaft sprocket
ecu.vhd
controller.vhd
crankshaft
sprocket
ignition
rst
Fig. 3: Top dead center positioning with respect to the timing
marks, in addition to four other positions of the crankshaft.
Assume that the timing belt provides a 1:2 ratio between the
camshaft and crankshaft sprockets, meaning that for a single
revolution of the camshaft, the crankshaft turns over twice.
Cyl. 1
2
3
3
4
3
cps
cylinder14.vhd
en
clk
counter[4..0]
counter[4..0]
vi
vi[3]
vi[3..0]
ignition
vo
vo[3]
vo[3..0]
advance
sp
sp[3]
sp[3..0]
fi
fi[3]
fi[3..0]
counter[4..0]
vi
vi[2]
ignition
vo
vo[2]
advance
sp
sp[2]
fi
fi[2]
counter[4..0]
vi
vi[1]
ignition
vo
vo[1]
advance
sp
sp[1]
fi
fi[1]
counter[4..0]
vi
vi[0]
ignition
vo
vo[0]
advance
sp
sp[0]
fi
fi[0]
retard
cylinder23.vhd
advance
retard
retard
cylinder23.vhd
1
1
retard
cylinder14.vhd
Fig. 4: Illustration of top dead center positioning in a typical
four-cylinder engine. Note that cylinder 1 is closest to the front
of the vehicle.
retard
In a typical fuel-injected controller, you can also “advance
timing” or “retárd timing”, which adjusts where in the combustion cycle the spark plug fires. Note that the spark plug
only fires for a single pulse of the CPS. When you advance
the timing, the spark plug fires once cycle sooner than normal,
while when you retard the timing, the spark plug fires one
cycle after it normally would.
Fig. 5: Engine cycle, annotated with the individual component
on and off states (VI: intake valve, VO: exhaust valve, SP: spark
plug, and FI: fuel injectors). TDC indicates the top dead center
position.
The inputs to the top-level entity (engine controller, ecu.vhd)
should be:
•
•
•
•
cps : STD_LOGIC, crank position sensor. Expect 12
pulses of equal length per a single crankshaft revolution.
ignition : STD_LOGIC, enable. This is your chance to
synchronize everything to top dead center positioning.
When this pin is high, the engine should be operating;
as it is tied to a reset through an inverter, when pulled
low, the engine should come back to top dead center
immediately.
retard : STD_LOGIC, signal to retard spark timing,
meaning that the spark will happen 1 CPS pulse after
the supposed spark timing.
advance : STD_LOGIC, signal to advance spark timing,
meaning that the spark will happen 1 CPS pulse before
the supposed spark timing (note that retard and advance
signals will never be high at the same time).
CEC220 LAB #F: SPRING 2018
Outputs of this entity will be as follows (element 0 of any
vector outputs corresponds to cyl. 1, closest to the front of the
vehicle):
•
•
•
•
vi : STD_LOGIC_VECTOR (3 downto 0), intake valve
outputs for each of the cylinders.
vo : STD_LOGIC_VECTOR (3 downto 0), exhaust valve
outputs for each of the cylinders.
sp : STD_LOGIC_VECTOR (3 downto 0), spark plug
outputs for each of the cylinders.
fi : STD_LOGIC_VECTOR (3 downto 0), fuel injector
outputs for each of the cylinders.
3
F.3 SAMPLE SIMULATIONS
Below are some sample simulations, showcasing the ECU
functionality. Note the shifting of the spark plug firing positions, depending on whether the timing is advanced or
retarded.
The lower level entities should be named as follows:
•
•
•
controller.vhd (inputs: en, rst, clk; outputs:
counter).
cylinder14.chd (inputs: counter, ignition, advance,
retard; outputs: vi, vo, sp, fi).
cylinder23.vhd (inputs: counter, ignition, advance,
retard; outputs: vi, vo, sp, fi).
Fig. 6: Normal operation.
Fig. 7: Timing advance.
Fig. 8: Timing retard.
© Akhan Almagambetov
04/06/2018 Embry-Riddle Aeronautical University (Prescott, AZ)
4
ENGINE CONTROLLER DESIGN
F.4 DELIVERABLES
F.6 ACADEMIC INTEGRITY
All of the files above (ecu.vhd, cylinder14.vhd, and cylinder23.vhd, plus a testbench (tb.vhd) and the corresponding
simulation that showcases every aspect of your design (including advance and retard functionality), printed directly from
Vivado and as ZIP file. Each file should include:
Any incidence of academic integrity violations (i.e., copying
code, which is super-easy to spot), will be dealt with very
harshly. You will get an automatic zero on this assignment
and I will recommend a failing grade in the class to the
chair of the department and the dean of the college, in
addition to a letter of reprimand being placed in your
permanent student record. All work that you submit for this
project must be entirely yours, from start to finish.
——
Lastname, Firstname (Sort #000)
201810.CEC220.PC04
Final Design Project: Engine Controller Design
Due: W 25-Apr-2018 1300
Description: top-level module ECU.VHD (modify this
description, based on the file you are
submitting).
All of your ports should contain the first three letters
of one of your group members, following an underscore
(i.e., counter_ALM). This should also be reflected in your
simulation(s).
F.5 GRADING
The following grading rubric will be applied (subject to
change, but it will provide a guide on what to focus when
designing your project):
•
•
•
•
•
•
No syntax errors, code synthesizes without errors, all of
the files included, correct hierarchy using components
and port maps, headers included on every file: +15 pts.
Correct valve timing: +20 pts.
Correct spark plug timing: +15 pts.
Correct fuel injector timing: +10 pts.
Retard/advance functionality: +10 pts/ea (+20 pts total).
Simulation and test bench showcases every aspect of
design functionality (+20 pts).
Any project submitted in Canvas and in hardcopy past
1300/1400 hrs (depending on your section) on the due date
will get a zero. If you only submit a hardcopy or only a digital
copy, you will get 50% of the total points you score.
Note that I will run your code against my self-checking
testbench to verify functionality. Hence, all of the signal names
should be exactly what is given in the “Design” section of
this requirements document. Any deviation from the required
naming conventions will adversely impact your grade.
Any code that you submit will be run through a code plagiarism checker, which is amazingly good at picking out
copied code (it was designed by a patent attorney/engineer,
who serves as an expert witness in Apple/Android copyright
infringement cases.. the guy is good at what he does, no joke).

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